1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device having logic circuitry integrated therewith and a control method therefor.
2. Description of the Background Art
FIG. 101 is a plan view representing a pin configuration of a 64 Mbit synchronous dynamic random access memory (SDRAM) with a 16 bit word configuration.
FIG. 102 is a table representing terminal names of SDRAM and their functions.
Referring to FIGS. 101 and 102, a prior art SDRAM is housed in, for example, a package with 54 pin terminals including a terminal CLK to which a master clock is inputted, a terminal CKE to which a clock enable signal is inputted, a terminal/CS to which a chip select signal is inputted, a terminal/RAS to which a row address strobe signal is inputted, a terminal/CAS to which a column address strobe signal is inputted and a terminal/WE to which a write enable signal is inputted.
A prior art SDRAM further has terminals DQ0 to DQ15 supplying/receiving a data I/O signal, a terminal DQM (U/L) through which an output disable signal/a write mask signal are inputted/outputted, terminals A0 to A11 to which an address is inputted, terminals BA0 and BA1 to which a bank address is inputted, a terminal VDD supplied with a power source, a terminal VDDQ supplied with an output power source, a terminal VSS provided with a ground potential and a terminal VSSQ provided with an output ground potential.
The terminals are configured such that as shown in FIG. 101, the data I/O terminals and power sources are disposed between the first and thirteenth pins, and between the forty-second and fifty-fourth terminals; the control signals and the clock signal are disposed between the fifteenth and nineteenth pins, and between the thirty-seventh and thirty-ninth pins; and the address pins are disposed between the twentieth and thirty-fifth pins. Such a terminal configuration is at a level of general versatility and also well used in a substrate on which a system including a memory is mounted.
FIG. 103 is a block diagram representing a configuration of a prior art logic integrated dynamic random access memory hereinafter referred to as DRAM).
Referring to FIG. 103, a DRAM 504 and a logic 508 are integrated on a chip 501 and provided with terminals for inputting or outputting control signals /RAS, /CAS, . . . , /CS for access to the DRAM, an address signal ADD and a data signal DATA.
In the chip 501, further included are control pins CTR0 and CTR1 unique to a logic, a terminal to which inputted is a request signal REQ requesting access to the logic, and a terminal for outputting a strobe signal STRB for notifying the outside that the logic completes a processing.
Since in the prior art, pins unique to the logic 508 were provided in order to control the logic 508, the number of pins increased compared with a general purpose DRAM as shown in FIG. 101; or in order to compose a system on a board, a dedicated controller for controlling a logic integrated DRAM had to be provided. Hence, a general versatility such as to be connected to an ordinary microcomputer was lost, or specific commands were required in a microcomputer for controlling the system.
It is accordingly an object to provide a semiconductor integrated circuit device on which integrated are memory circuitry and logic circuitry that can be controlled by a control method similar to that of a general purpose DRAM.
It is another object to provide a semiconductor integrated circuit device, on which integrated are memory circuitry such as DRAM and logic circuitry, capable of supplying/receiving a result of a prescribed logical operation performed on data stored in the memory circuitry through an interface easy to be externally handled.
The present invention will be summarized: The present invention is a semiconductor integrated circuit device and includes a terminal group, a memory cell array and logic circuitry.
The terminal group receives extremely supplied control signal, address signal and data. The memory cell array, according to the control signal, stores storage data in an area specified by the address signal. When the address signal specifies a predetermined area, the logic circuitry performs an logic operation according to at least one of the control signal, the address signal and the data supplied from the terminal group. The logic circuitry switching data to be processed in the logic operation according to the control signal between the storage data already stored in the memory cell array and data supplied from the terminal group.
In another aspect of the present invention, a semiconductor integrated circuit device comprises a terminal group, a memory cell array, and logic circuitry.
The terminal group has a predetermined number of pin terminals and receives externally supplied control signal, address signal and data.
The memory cell array, according to the control signal, stores storage data in an area specified by the address signal.
The logic circuitry performs a logic operation according to at least one of the control signal, the address signal and the data supplied from the terminal group when the address signal specifies a predetermined area, The logic circuitry switches data to be processed in the logic operation according to the control signal between the storage data already stored in the memory cell array and data supplied from the terminal group,
The predetermined number is identical with the number of pin terminals of an available DRAM.
Hence, an advantage of the present invention is that the logic circuitry integrated can be controlled according to a sequence similar to that according to which data, an address and a control signal are given to a general purpose memory, and the system can be obtained without altering an existing system greatly and easy to be controlled. Furthermore, an advantage of the present invention is that a semiconductor integrated circuit on which integrated are memory circuitry and logic circuitry can supplies/receives a result of a prescribed logical operation on data stored in the memory circuitry at a high speed through an interface easy to be externally handled.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.